Toshiba, IBM and AMD develop smallest, most stable FinFET SRAM to date

[4T7]

Toshiba, IBM and AMD have announced the joint development of a new SRAm cell with an area of only 0.128 square micrometers.

"SRAM cells are key components in integrated circuits and are an important technology metric in the semiconductor industry," Jeff Couture of IBM said. "This highlights the companies' ability to use finFET transistors to shrink the SRAM cell to dimensions needed for next-generation applications. The work described by the three companies demonstrates that these non-planar, fin-shaped transistors show promise for microprocessors and other chips produced at 32-nanometer, 22-nanometer and smaller dimensions."

Couture also explained that the development methods utilised by researchers reduced some of the variability that occurs during the production of conventional planar transistors at 32nm and smaller technology levels. "SRAM characteristics were simulated for a cell area at about half the size of this smallest reported cell – 0.063μm2 – equal to or smaller than dimensions required for 22nm scaling. The researchers concluded that more stable SRAM operation will be expected by using FinFET devices in the 22nm node," added Couture.

The cell, developed with a high-k/metal gate (HKMG) material, offers a number of advantages over planar-FET cells for future technology generations. SRAM cells are often used as circuit components in most systems-level, large-scale integrated circuits such as microprocessors. The creation of smaller SRAM cells will help provide smaller and faster processors that consume less power.

Source

[MetalheadGautham]

This would mean AMD can release higher L1, L2 and L3 caches on their CPUs. Great news.