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Originally Posted by varunprabhakar
but isnt it supposed to work at 400mhz??
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see in one clock cyle there is one rising edge and a falling edge.......
It achieves greater bandwidth than the preceding single-data-rate SDRAM by transferring data on both the rising and falling edges of the clock signal (double pumped). This effectively nearly doubles the transfer rate without increasing the frequency of the front side bus. Thus a 100 MHz DDR system has an effective clock rate of 200 MHz when compared to equivalent SDR SDRAM, the “SDR” being a retrospective designation.